`timescale 1ns / 1ps

module hdmi_show_pic_tb ();

reg               IN_CLK_50M;
reg   [7:1]       PB;

wire              HDMI_CLK;
wire              HDMI_HS;
wire              HDMI_VS;
wire              HDMI_EN;
wire  [23:0]      HDMI_D;

wire               IIC_SDA;
wire               IIC_SCL;

hdmi_show_pic hdmi_show_pic_inst (
	.IN_CLK_50M(IN_CLK_50M),
	.PB(PB),
	
	.HDMI_CLK(HDMI_CLK),
	.HDMI_HS(HDMI_HS),
	.HDMI_VS(HDMI_VS),
	.HDMI_EN(HDMI_EN),
	.HDMI_D(HDMI_D),
	
	.IIC_SDA(IIC_SDA),
	.IIC_SCL(IIC_SCL)
);

initial IN_CLK_50M = 1;
always #10 IN_CLK_50M = ~IN_CLK_50M;

endmodule
